With a great increase in the capacity of optical disk storage equipment, there is an urgent need to increase write speed. For optical disk drive devices in which data is recorded on optical disks (data recording media) by optical modulation of laser beam, necessary are a one-beam overwrite technique and a technique for controlling optical modulation waveforms by multi-pulsing and multi-leveling the waveforms in order to control the shape of a recording mark, which is required to enhance recording density. To further enhance high-speed recording and high-density recording, even a higher data transfer rate, pulse splitting into sub-pulses with even shorter width, and increase in the number of power levels will be required in future.
For example, a write strategy technique which is applied to DVD-RW uses a plurality of laser pulses with three different power levels as is illustrated in a write strategy example shown in FIG. 2. These three power levels are write power Pw, erase power Pe, and bottom/read power Pb in descending order of level. When an optical disk is irradiated by laser beam with the above write power Pw, the recording film subject to the laser beam irradiation in the optical disk melts. Then, as the optical disk is rapidly cooled, the irradiated portion of the recording film becomes amorphous and its light reflectivity becomes low. This portion is used as a recording mark. When the optical disk is irradiated by laser beam with the erase power Pe, the recording film is crystallized. The amorphous portion of the optical disk before the laser beam irradiation becomes crystalline and the crystal portion thereof remains crystalline. Thereby, the recording mark can be removed. Laser beam with the read power Pb is used to read a data signal recorded on the optical disk.
Because a recording mark is written on a medium by a train of write strategy pulses when recording, accuracy of timing of the first and last write strategy pulses is important to enhance the accuracy of the recording mark edges. Pulse splitting into even shorter sub-pulses and increase in the number of power levels become more difficult as write speed rises in terms of two viewpoints: accuracy of timing at a high speed and synchronization of a plurality of pieces of data. Clock frequencies of 2-3 GHz have heretofore been required and timing accuracy of write pulses has been obtained by setting time to start and time to stop each pulse by using a plurality of fixed delay lines 16-1, 16-2, . . . as is shown in FIG. 3 or by using the output from a tap that is proximate to a target position, one of the taps of closely spaced steps of a multistage delay block, and thereby the foregoing write pulses are generated. In JP-A No. 243589/1994, a technique in which a clock is generated by delaying a clock from a phase locked loop (PLL) is described. In the data communications area, a parallel-to-serial conversion technique using a multiplexer is applied, as is described in JP-A No. 152728/2003.    [Patent Document 1] JP-A No. 243589/1994    [Patent Document 2] JP-A No. 152728/2003